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DSP56311 Overview
Chapter 7, Enhanced Synchronous Serial Interface (ESSI) . Enhancements, data and
control signals, programming model, operating modes, initialization, exceptions, and
GPIO.
Chapter 8, Serial Communication Interface (SCI) . Signals, programming model,
operating modes, reset, initialization, and GPIO.
Chapter 9, Triple Timer Module . Architecture, programming model, and operating modes
of three identical timer devices available for use as internals or event counters.
Chapter 10, Enhanced Filter Coprocessor (EFCOP) — Structure and function of the
EFCOP, including features, architecture, and programming model; programming topics
such as data transfer to and from the EFCOP, its use in different modes, and examples of
usage.
Appendix A, Bootstrap Code . Bootstrap code and equates for the DSP56311.
Appendix B, Programming Reference . Peripheral addresses, interrupt addresses, and
interrupt priorities for the DSP56311; programming sheets listing the contents of the
major DSP56311 registers for programmer’s reference.
1.2 Manual Conventions
This manual uses the following conventions:
Bits within registers are always listed from most significant bit (MSB) to least significant
bit (LSB).
Bits within a register are indicated AA[n – m], n > m, when more than one bit is involved
in a description. For purposes of description, the bits are presented as if they are
contiguous within a register. However, this is not always the case. Refer to the
programming model diagrams or to the programming sheets to see the exact location of
bits within a register.
When a bit is “set,” its value is 1. When a bit is “cleared,” its value is 0.
The word “assert” means that a high true (active high) signal is pulled high to V CC or that
a low true (active low) signal is pulled low to ground. The word “deassert” means that a
high true signal is pulled low to ground or that a low true signal is pulled high to V CC . See
Table 1-1 .
DSP56311 User’s Manual, Rev. 2
1-2
Freescale Semiconductor
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